SmartDO

Using SmartDO for Optimizing TDR/EMC of PCB with Cutting-Edge Computing Efficiency

Optimizing electromagnetic compatibility (EMC) and TDR is a critical challenge for ensuring high-performance printed circuit boards (PCBs). Leveraging tools with Cutting-Edge Computing Efficiency such as SmartDO, designers can now efficiently improve the overall quality of their designs.
In this article, we will show you how SmartDO solved such designproblems with 39 design variables utilizing Cutting-Edge Computing Efficiency.

SmartDO: A Powerful Smart Design Solution for TDR/EMC Optimization

SmartDO is a push-button, general purpose multi-physics and multidisciplinary optimization tool designed to address complex electromagnetic and impedance issues in PCB designs. Using advanced algorithms, it can optimize TDR impedance, return loss (RL), and insertion loss (IL), in high computing efficiency.

Tackling Complex TDR/EMC Optimization with Cutting-Edge Computing Efficiency of SmartDO

Figure 1 to 4 shows the 39 design variables of the shielding vias in a PCB to optimize, for achieving the TDR/EMC performance requirement. They include via sizes, trace widths, and clearance, with the following design requirement.

• TDR Impedance should be as close to 50Ω as possible
• Via distance > 75 um
• Return Loss (RL) < -20 dB
• Insertion Loss (IL) < 0 and > -0.5 dB

Figure 1. Design Variables of the Shielding Vias (1).


Figure 2. Design Variables of the Shielding Vias (2).


Figure 3. Design Variables of the Shielding Vias (3).


Figure 4. Design Variables of the Shielding Vias (4).



Figure 5 Shows the geometry change of the shielding vias after optimized by SmartDO. SmartDO executed around 600 calls to an external FEA program (ANSYS HFSS) to deliver significant improvements:

• TDR Impedance stayed within the target of 50±10% Ω
• Via distance satisfied
• Return Loss (RL) improved by 67.3%, dropping below -20 dB.
• Insertion Loss (IL) improved by 51.6%, ensuring better signal integrity.

Figure 5. Geometry Change of the Shielding Vias after Optimized by SmartDO.



Figure 6 to 8 shows the TDR/EMC performance curve before and after SmartDO optimization.


Figure 6. EMC Performance Curve Before and After SmartDO Optimization (1).


Figure 7. EMC Performance Curve Before and After SmartDO Optimization (2).


Figure 8. EMC Performance Curve Before and After SmartDO Optimization (3).



The SmartDO Advantage




SmartDO efficiently handled the optimization of 39 design variables, requiring around 600 ANSYS HFSS FEA simulations. This remarkable efficiency, despite the problem’s complexity, led to significant improvements in both Return Loss (RL) and Insertion Loss (IL). With unique Smart Design technology like global nonlinear programming, AI-Powered SmartLearning and S.A.F.E.D., SmartDO ensured fast, accurate results with high computing efficiency.

Reference

• Using SmartDO for the design optimization of electronic system multiphysics phenomenon (Dr. Bill Chen /R&D Dept., Unimicron Technology Corp.), 2024 SmartDO Conference for Smart Design (Hsingchu City, Taiwan, Nov 24, 2024)

For more information about SmartDO, please contact us.